Method of lithographic image alignment for use with a dual mask exposure technique

ABSTRACT

Methods of fabricating an integrated circuit on a wafer using dual mask exposure lithography is disclosed. Improved mask image alignment between a first mask image and a second mask image of a dual mask exposure technique can be achieved by aligning the second mask image to a latent image created by an exposure using the first mask image.

TECHNICAL FIELD

The present invention relates generally to the field of integratedcircuit manufacture and, more particularly, to a method of lithographicimage alignment for use with a dual mask exposure technique.

BACKGROUND

The formation of various integrated circuit (IC) structures on a waferoften relies on lithographic processes, sometimes referred to asphotolithography, or simply lithography. For instance, patterns can beformed from a photo resist layer by passing light energy through a mask(or reticle) having an arrangement to image the desired pattern onto thephoto resist layer. As a result, the pattern is transferred to the photoresist layer. In areas where the photo resist is sufficiently exposedand after a development cycle, the photo resist material can becomesoluble such that it can be removed to selectively expose an underlyinglayer (e.g., a semiconductor layer, a metal or metal containing layer, adielectric layer, etc.). Portions of the photo resist layer not exposedto a threshold amount of light energy will not be removed and serve toprotect the underlying layer. The exposed portions of the underlyinglayer can then be etched (e.g., by using a chemical wet etch or a dryreactive ion etch (RIE)) such that the pattern formed from the photoresist layer is transferred to the underlying layer. Alternatively, thephoto resist layer can be used to block dopant implantation into theprotected portions of the underlying layer or to retard reaction of theprotected portions of the underlying layer. Thereafter, the remainingportions of the photo resist layer can be removed.

There is a pervasive trend in the art of IC fabrication to increase thedensity with which various structures are arranged. As a result, thereis a corresponding need to increase the resolution capability oflithography systems. Various resolution enhancement techniques (RET)have been proposed to aid in the lithography process. For example,alternating phase shift masks and full phase shift masks have beenemployed. As another example, dipole illumination sources have beenused.

In conjunction with these resolution enhancement techniques dual maskexposures have been used. An example dual mask exposure can involveexposing a photo resist layer with a first mask of a mask pair and thenseparately exposing the same photo resist layer with a second mask ofthe mask pair. Variations to this basic dual mask exposure techniqueexist and will be discussed in greater detail in subsequent sections.

Conventionally, integrated circuit fabrication involves exposing thewafer to multiple mask images. To achieve an acceptable overlay amongthe physical layers having patterns defined by these mask images,alignment of each mask within a given tolerance should be achieved. Asis known in the art, overlay relates the lateral positioning betweenphysical layers comprising an integrated circuit. If the layers are notproperly aligned with each other, the performance of the devices of theintegrated circuit can be compromised. In this situation, it is likelythat the integrated circuit, if not the entire wafer (upon whichmultiple integrated circuits may be fabricated), may be unusable.

In conventional wafer processing mask image alignment is achieved byestablishing a zero mark on the wafer. Typically, the zero mark is thefirst structure printed onto the wafer. The zero mark can be carefullyoptimized to provide a reference point to which each exposure (e.g., allmask images) are aligned. It is noted that some physical layers (e.g., ametal layer) may adversely impact the use of the zero mark forsubsequent mask images and, in this situation, a new zero mark can beestablished on the wafer for use in aligning subsequent mask images.

Conventionally, each mask image of a dual mask exposure is aligned tothe zero mark. In some situations, this method of mask image alignmentdoes not result in satisfactory alignment between the first mask imageand the second mask image of the dual mask exposure.

Accordingly, there exists a need in the art for techniques of improvingalignment in dual mask exposures.

SUMMARY OF THE INVENTION

According to one aspect of the invention, the invention is directed to amethod of fabricating an integrated circuit on a wafer using dual maskexposure lithography. The method can include forming a photo resistlayer over the wafer; aligning the wafer with respect to a lithographysystem using a reference mark that is formed on the wafer; exposing thephoto resist layer with a first mask image defined by a first mask usingthe lithography system, the first mask image including a latent imagealignment mark that is transferred to the photo resist layer;re-aligning the wafer with respect to the lithography system using thelatent image alignment mark resulting from the exposure to the firstmask image; and exposing the photo resist layer with a second mask imagedefined by a second mask using the lithography system.

According to another aspect of the invention, the invention is directionto a method of fabricating a hard mask layer on a wafer using dual maskexposure lithography. The method can include forming a first photoresist layer over a layer of hard mask material that is formed over thewafer; aligning the wafer with respect to a lithography system using areference mark that is formed on the wafer; exposing the first photoresist layer with a first mask image defined by a first mask using thelithography system, the first mask image including a latent imagealignment mark that is transferred to the photo resist layer; developingthe first photo resist layer; etching the hard mask material layer totransfer a layout of the first mask image to the hard mask materiallayer, the transferred layout including the latent image alignment mark;re-aligning the wafer with respect to the lithography system using thelatent image alignment mark; and exposing wafer with a second mask imagedefined by a second mask using the lithography system.

BRIEF DESCRIPTION OF DRAWINGS

These and further features of the present invention will be apparentwith reference to the following description and drawings, wherein:

FIG. 1 is a schematic block diagram of an example integrated circuitprocessing arrangement;

FIG. 2 is a top view of an example semiconductor wafer that can beprocessed using the integrated circuit processing arrangement of FIG. 1;

FIG. 3 is a flow diagram of an example technique for aligning maskimages of a dual mask exposure;

FIG. 4 is an enlarged partial top view of the wafer of FIG. 2 in anintermediate stage of integrated circuit fabrication; and

FIG. 5 is an enlarged partial top view of the wafer of FIG. 2 in anotherintermediate stage of integrated circuit fabrication.

DISCLOSURE OF INVENTION

In the detailed description that follows, similar components have beengiven the same reference numerals, regardless of whether they are shownin different views and/or embodiments. To illustrate the various aspectsof the present invention(s) in a clear and concise manner, the drawingsmay not necessarily be to scale and certain features may be shown insomewhat schematic form. Features that are described and/or illustratedwith respect to one embodiment may be used in the same way or in asimilar way in one or more other embodiments and/or in combination withor instead of the features of the other embodiments.

The description herein is presented in the exemplary context offabricating a wafer having an integrated circuit (IC) formed thereon.Example ICs include general purpose microprocessors made from thousandsor millions of transistors, a flash memory array or any other dedicatedcircuitry. One skilled in the art will appreciate that the methods anddevices described herein can also be applied to the fabrication of anyarticle manufactured using lithography, such as micromachines, diskdrive heads, gene chips, micro electromechanical systems (MEMS) and soforth.

The apparatus and methods described herein can provide for improvingmask image alignment between a first mask image and a second mask imageof a dual mask exposure technique. Briefly, alignment can be improved byaligning the second mask image to a latent image created by an exposureusing the first mask image. As should be appreciated, the terms reticleor photomask may be used interchangeably with the term mask.

The term mask image will be used to refer to the illuminated patternincident on the wafer resulting from an exposure of the wafer using aparticular mask. The term layer is sometimes used in the art to describea mask image, but the term layer will be used herein to refer to aphysical layer of material, such as a photo resist layer, a dielectriclayer, a polysilicon layer, a source/drain layer, etc.

Dual mask exposure, as used herein, involves exposing a photo resistlayer with a first mask image of a mask pair to generate a first maskimage and then separately exposing the same photo resist layer with asecond mask layer of the mask pair to generate a second mask image. As aresult, the exposures using each of the masks (e.g., the first andsecond mask images) are embodied into the same physical layer of photoresist. As one skilled in the art will appreciate, variations to theforegoing basic dual mask exposure technique exist and should beconsidered to fall within the scope of the term “dual mask exposure.” Anexample variation can include using an additional mask image or imagesapplied to the photo resist material (e.g., a triple mask exposure orhigher order mask exposure).

Another example variation to dual mask exposure includes partially orfully developing, or otherwise processing, the photo resist layerbetween exposures using the first dual exposure mask and the second dualexposure mask.

Another example variation includes the use of a stack of photo resistlayers. Each mask image may be applied to all of the sublayers of thephoto resist layer or any one of the mask images may be applied to lessthan all of the photo resist layers. In this variation, one or morephotoresist layers may be deposited after a particular mask image isgenerated.

Yet another example variation includes defining the layout of a hardmask (e.g., a nitride layer formed over an underlying layer to beprocessed with the nitride layer as a protective mask layer for thatunderlying layer) using two or more mask images. For example, a firstphoto resist layer can be formed over the hard mask layer and exposedwith the first mask image. The first photo resist layer can be developedand the hard mask layer can be processed in a desired manner.Thereafter, a second photo resist layer can be formed over the hard masklayer (the first photo resist layer optionally can be removed) andexposed with the second mask image. The second photo resist layer can bedeveloped and the hard mask layer can be processed again. Thereafter,the underlying layer can be processed as desired using the hard mask toprotect certain areas of the underlying layer.

Dual mask exposure techniques can be used in conjunction with variousresolution enhancement techniques (RET) intended to increase theresolution capability of lithography systems. For example, the masks ofthe dual mask exposure may include alternating phase shift masks and/orfull phase shift masks. As another example, a dipole illumination sourcemay be used to provide radiation incident on the masks of the dual maskexposure.

Dual mask exposure techniques can be used in a variety of manners toenhance wafer processing and can include, for example, creating acomposite mask image from the individual mask images of each mask in thedual mask exposure. For example, one mask image can be used to definecritical dimension features and the other mask image can be used todefine non-critical dimension features. As another example, one maskimage can be used to define images in one direction (e.g., the Xdirection) and the other mask image can be used to define images inanother direction (e.g., the Y direction). Dual mask exposures can beused in connection with the formation of a wide variety of wafer layers,including, but not limited to, a polysilicon layer, a source/drain layerand so forth.

Turning initially to FIG. 1, illustrated is a schematic block diagram ofan exemplary integrated circuit processing arrangement that includes alithography system 10 used to image a pattern onto a wafer 12, or aregion thereof. The system 10 can be, for example, a step-and-repeatexposure system or a step-and-scan exposure system, but is not limitedto these example systems. The system 10 can include a light source 14for directing light energy 16 towards a mask 18 (sometimes referred toas a reticle). The light energy 16 can have, for example, a deepultraviolet (DUV) wavelength (e.g., about 248 nm or about 193 nm), avacuum ultraviolet (VUV) wavelength (e.g., about 157 nm), or an extremeultraviolet (EUV) wavelength (e.g., about 13.4 nm).

The mask 18, which can be mounted on a stage or chuck (not shown)selectively blocks light energy 16 (or, in the case of an EUVwavelength, selectively reflects radiation) such that a light energypattern 20 defined by the mask 18 is transferred towards the wafer 12.An imaging subsystem 22, such as a stepper assembly or a scannerassembly, sequentially directs the energy pattern 20 transmitted by themask 18 to a series of desired locations on the wafer 12. The imagingsubsystem 22 may include a series of lenses and/or reflectors for use inscaling and directing the energy pattern 20 towards the wafer 12 in theform of an imaging (or exposure) light energy pattern 24.

The wafer 12 may be mounted on a wafer stage 25. In one embodiment, thewafer stage 25 can be moved relative to the imaging subsystem 22 so asto place a desired portion of the wafer 12 in the path of the exposurepattern 24. Alternatively, the imaging optics can be movable and/or theexposure pattern can be optically retargeted. As will be discussed ingreater detail below, between each sequential illumination of the wafer12 with the exposure pattern 24, alignment of the exposure pattern 24and the wafer 12 can be established with the use of reference marks(sometimes referred to as scribe marks if the reference marks are placedin scribe lines of the wafer).

To assist in aligning the wafer 12 with respect to the exposure pattern,the lithography system 10 can include an alignment subsystem 26. Thealignment subsystem 26 may be a part of a general control system 28 forthe lithography system 26. Wafer alignment subsystems are relativelywell known in the art and, therefore, the details of such systems aredescribed only briefly and/or omitted. In one example, the alignmentsubsystem 26 includes wafer alignment sensors 29, sometimes referred toas microscopes. The alignment sensors 29 can have an optic axis parallelto (e.g., off axis) or coincident with (e.g., axial) the optic axis ofthe imaging subsystem 22. Each alignment sensor 29 can image a laserlight spot (not shown) onto the wafer 12, for example. The laser spot isradiation of a wavelength that should not activate the photosensitiveagent (photo resist material) that is disposed on the wafer 12. Also,each alignment sensor 29 can have a photo-element (not shown) forreceiving scattered light and/or diffracted light from the referencemarks printed on the wafer 12. The alignment sensors 29 can each includesystems for synchronizing and rectifying the photoelectric signal outputby the photo-elements, respectively, at the vibration period of thelight spot(s) and for outputting an alignment signal corresponding toalignment mark deviation relative to the center of vibration of thelight spot(s). It is to be appreciated that wafer alignment positioningsystems are evolving rapidly and any suitable alternative positioningsystem (e.g., a through the lens system) may be employed.

Turning now to FIG. 2, a top view of an example semiconductor wafer 12that can be processed using the lithography system 10 is shown. Thewafer 12 comprises a plurality of die regions 30 that are delineated onthe wafer by scribe lines 32.

With additional reference to FIG. 3, a flow diagram of an exampletechnique, or process 34, for aligning mask images of a dual maskexposure is shown. The process 34 can be thought of as depicting stepsin a method. The flow diagram includes a number of process blocksarranged in a particular order. Since lithographic processing and dualmask exposure techniques in particular, can vary widely, the illustratedprocess 34 is merely exemplary. As should be appreciated, manyalternatives and equivalents to the illustrated process 34 may exist andsuch alternatives and equivalents are intended to fall with the scope ofthe claims appended hereto. Alternatives may involve carrying outadditional steps or actions not specifically recited and/or shown,carrying out steps or actions in a different order from that recitedand/or shown, and/or omitting recited and/or shown steps. Alternativesalso include carrying out steps or actions concurrently or with partialconcurrence.

As should as be apparent, the process 34 is described for a dual maskexposure of a particular die area 30, or other region of the wafer 12,to be exposed by a corresponding pair of mask images (e.g., a secondmask image exposed onto the same area as was previously exposed by afirst mask image). Between certain processing steps described herein,the wafer 12 may be moved to expose other areas of the wafer 12 (e.g.,following a step and repeat technique or scan and repeat technique) orto process the wafer 12 (e.g., to partially develop photo resistmaterial).

With additional reference to FIG. 4, the process 34 can begin in block36 where reference marks 38 are created on the wafer 12. FIG. 4 is anenlarged partial top view of a portion of the wafer 12 identified bycircle A of FIG. 2. The creation of reference marks 38 are relativelywell know in the art and will not be described in great detail. In theillustrated example, the reference marks 38 are disposed within thesacrificial scribe areas 32 of the wafer 12 (e.g., where the wafer 12will be sawed apart to obtain individual integrated circuit chips fromthe wafer 12) and can be referred to as scribe marks. The referencemarks 38 can include zero marks (e.g., marks that are among the firststructures printed on the wafer) or marks associated with a currentprocess. Also, the reference marks 38 need not be formed in the scribelines 32 and can be formed within the die regions 30.

The reference marks 38 can serve as alignment reference points that areused by the alignment subsystem 26 to position the wafer 12 relative tothe exposure pattern 24 before various exposures of the wafer 12, withthe exception of certain dual mask exposures as described in greaterdetail below.

Following formation of the reference marks 38, the wafer 12 can beprocessed up to the point that a dual mask exposure is desired. Theprocessing may include configuring the wafer 12 for the formation ofbulk type devices or semiconductor-on-insulator (SOI) devices (e.g.,having a semiconductor layer formed over an insulating layer such as aburied oxide layer that is, in turn, formed over a handle wafer).Example processing in block 40 can include forming various layers(including patterned and unpatterned layers), forming isolation regions,forming structures and/or implanting various regions. As one skilled inthe art will appreciate, the processing of block 40 can differ greatlydepending on the specific devices being formed on the wafer 12.

During the processing of block 40, it is contemplated that lithographicpatterning of one or more photo resist layers may be employed (e.g., thelayers of photo resist corresponding to a physical layer of the wafer tobe etched, implanted or otherwise processed). Each layer of photo resistcan be exposed to an exposure pattern 24. In preparation for theexposure, the wafer 12 can be aligned to the imaging subsystem 22 usingthe reference marks 38 as reference points.

Once the wafer 12 has been processed up to the point where a dual maskexposure is desired, a dual mask photo resist layer can be deposited onthe wafer 12 in block 42. With additional reference to FIG. 5, shown isan enlarged partial top view of the wafer 12 with a dual mask photoresist layer, or photo resist layer 44, formed thereon. FIG. 5 is anenlarged partial top view of a portion of the wafer 12 identified bycircle A of FIG. 2. If desired, block 42 can include additionaldepositions and/or processing associated with the photo resist layer 44.For example, a primer and/or bottom anti-reflective coating (BARC) layercan be formed over the wafer 12 prior to photo resist layer 44deposition and/or a coating or treatment can be applied over the photoresist layer 44.

In block 46 a first mask for imaging the wafer 12 as part of the dualmask exposure can be loaded into the lithography system 10. Thereafter,the wafer 12 can be aligned with respect to the imaging subsystem 22 inblock 48. In one embodiment, the alignment of block 48 is made using thereference marks 38.

After the wafer 12 has been aligned, the process 34 can continue inblock 50 where the photo resist layer 44 is imaged using the first maskto define the exposure pattern 24. The exposure pattern 24 defined bythe first mask can be considered a first mask image.

Portions of the first mask image can be used to define one or morelatent images 52 in the photo resist layer 44. As will be discussedbelow, the latent images 52 can be used to assist in aligning the wafer12 in preparation for an exposure using a second mask of the dual maskexposure. In the illustrated embodiment, the latent images 52 are formedin the areas defined by the scribe lines 32. Therefore, the latentimages 52 can be considered a category of reference marks or scribemarks. The latent images 52 need not be formed in the scribe lines 32and can be formed within the die regions 30.

The alignment sensors 29 of the alignment subsystem 26 can be configuredto detect the latent images 52. In one embodiment, two sets of alignmentsensors 29 can be provided such that one set is used when aligning thewafer 12 to the reference marks 38 and the other set is used whenaligning to the latent images 52.

In many situations, merely exposing conventional photo resist materialto an exposure dose may not result in latent images that are detectable(e.g., can be “seen”) by the alignment sensors 29. Accordingly,enhancements to the photo resist layer 44 can be made and/or processingof the exposure photo resist layer 44 can be carried out to enhancedetectability of the latent images 52 by the alignment sensors 29. Theenhancements and/or processing are selected to result in changes inoptical characteristics of the photo resist layer 52 that can bedetected by the alignment subsystem 26. These changes in opticalcharacteristics can include, for example, changing an amount ofreflected light energy associated with the latent image 52, defining anedge or other geometrical boundary associated with the layer image 52and so forth.

An example technique for enhancing detectability of the latent images 52can include adding compounds to the photo resist layer 44 duringformation in block 42 to alter the resist chemistry. When the photoresist layer 44 is exposed to the first mask image, the altered resistchemistry can change appearance in the locations upon which a thresholdamount of energy is incident. The appearance change need only bedetectable by the alignment subsystem 26, and specifically the alignmentsensors 29 (FIG. 1).

Another example technique for enhancing detectability includes using aphoto resist layer 44 comprised of two or more sublayers. The first maskimage can be used to pattern a top resist layer with a desired patternthat includes the latent images 52. The other sublayer(s) may also beexposed to the first mask image. Thereafter, the top resist layer(s) canbe developed or partially developed to create an edge or edges definingthe latent images 52 that are detectable by the alignment subsystem 26.In one embodiment, each resist sublayer optionally may have differentcharacteristics that allow for development or partial development of atop resist sublayer, such as wavelength sensitivity, exposure dosesensitivity, thicknesses, developer solubility, etc. In anotherembodiment, the top layer(s) are optimized to leave detectable latentimages 52 by exposure only. After development of the photo resist layer44, images from both mask images can then be realized.

As one skilled in the art will appreciate, the techniques for enhancinglatent image detectability are not limited to those specificallyidentified herein. For example, other known techniques exist forcreating an image in a photo resist layer without completely developingthe photo resist layer can be used.

The process 34 can continue in block 54 where a second mask for imagingthe wafer 12 as part of the dual mask exposure can be loaded into thelithography system 10.

Thereafter, in block 56 the wafer 12 can be aligned with respect to theimaging subsystem 22 in preparation for exposing the photo resist layer44 with a second mask image as defined by the second mask. The secondmask image corresponds to the first mask image so as to constitute adual mask exposure. The alignment of block 56 is made using the latentimages 52, the locations of which were defined by the first mask image.

Next, in block 58, the photo resist layer 44 is imaged using the secondmask to define an exposure pattern, or second mask image. Followingexposure by the second mask image, the photo resist layer 44 can bedeveloped in block 60. The developed photo resist layer 44 can include alayout defined by both the first and second mask images. This layout ofthe developed photo resist layer 44 can be used in connection withadditional processing of the wafer 12 in block 62. The processing of thewafer 12 can include processing a layer that underlies the photo resistlayer 44. For example, the underlying layer can be etched such that thelayout of the photo resist layer 44 is transferred to the underlyinglayer. In other examples, the photo resist layer 44 can be used toselectively block dopant implantation into the underlying layer or toselectively retard reaction of the underlying layer with a reagent.

After the photo resist layer 44 is no longer desired; the photo resistlayer 44 can be removed in block 64. Removal techniques, such as dryashing, are relatively well known in the art and will not be discussedin greater detail.

Processing of the wafer 12 can continue in block 66. The processing ofblock 66 can include depositing and/or patterning additional photoresist layers on the wafer 12. The additional photo resist layers can bepatterned using lithographic techniques where alignment of the wafer 12with respect to the imaging subsystem 22 is made by tracking thelocation of the reference marks 38.

The example process 34 as described above generally relates to a basicdual mask exposure technique. One with ordinary skill in the art willappreciate that the process 34 can be appropriately modified toaccommodate the wide variety of variations that fall within the scope ofdual mask exposures.

As an example modification, detectability of the latent images 52 can beenhanced by increasing their exposure. For example, the latent images 52can be exposed twice with the first mask. In another example, the latentimages 52 can be exposed with the first mask and then again with anoverlapping exposure.

As another example modification, a hard mask can be formed using thetechniques described herein. In one embodiment, a first photo resistlayer can be formed over a layer of hard mask material that is, in turn,formed over the wafer. The wafer can be aligned with respect to alithography system using a reference mark that is formed on the wafer.Thereafter, the first photo resist layer can be exposed with a firstmask image defined by a first mask using the lithography system. Thefirst mask image can include a latent image alignment mark that istransferred to the photo resist layer. Then, the first photo resistlayer can be developed and the hard mask material layer can be etched totransfer a layout of the first mask image to the hard mask materiallayer. The transferred layout can include the latent image alignmentmark. Thereafter, the wafer can be realigned with respect to thelithography system using the latent image alignment mark and the wafercan be exposed with a second mask image defined by a second mask usingthe lithography system.

Additional processing for making the hard mask layer can includedeveloping the photo resist and etching the hard mask material layer totransfer a layout of the second mask image to the hard mask materiallayer. Other processing can include forming a second photo resist layerover the layer of hard mask material after etching of the hard maskmaterial layer to transfer the layout of the first mask image to thehard mask material and/or removing the first photo resist layer beforeforming the second photo resist layer.

In the illustrated embodiments, the reference marks 38 have a plus sign(e.g., “+”) shape and the latent images 52 have an “x” shape. The shapeof reference marks 38 and/or latent images 52 can differ from thoseillustrated. For example, the latent images 38 can be patterned in theshape of a plus (“+”) sign similar to the illustrated reference marks38, rather than in the illustrated “x” shape. Other shapes can also beused for either or both of the reference marks 38 and the latent images52, including, for example, a square, a rectangle, a dash (e.g., “−”),and so forth.

The dual mask exposure technique described herein can result in lessalignment error between the first mask image and the second mask imagethan found in prior art techniques. In convention techniques, alignmenterror between the first mask image and the second mask image can be at amaximum when the first mask image is aligned to a maximum tolerablealignment error with respect to the reference mark 38 in a firstdirection and the second mask image is aligned to the maximum tolerablealignment error with respect to the reference mark 38 in a seconddirection opposite that from the first direction. Statistically, thistheoretical maximum alignment error rarely occurs and the alignmenterror between the first and second mask images can be computed using aroot sum squared approach (e.g., sum the square of each image'salignment error and take the square root of the total). In an examplewhere it is assumed that the maximum tolerable alignment error for aparticular mask image with respect to the alignment reference is 50nanometers (nm), the theoretical maximum alignment error will be 100 nm(e.g., 50 nm in opposite directions from the reference mark 38) and thestatistical maximum alignment error will be about 70 nm (e.g., thesquare root of the total of 50 nm squared plus 50 nm squared).

Without intending to be bound by theory; the alignment error using thedual mask exposure technique described herein should be less than theconventional theoretical or statistical results. In the dual maskexposure technique described herein, alignment error with respect to thereference mark 38 for the first mask image does not factor as being apart of the alignment error between the first mask image and the secondmask image. The second mask image is aligned to an image created by thefirst mask image (e.g., the latent image 52). Accordingly, the alignmenterror between the first mask image and the second mask image is simplythe alignment error of the second mask image with respect to thealignment reference for the second mask image, which is the latent image52 defined by the first mask image. In the example where it is assumedthat the maximum tolerable alignment error for a particular mask imagewith respect to the alignment reference is 50 nm, the maximum alignmenterror between the first mask image and the second mask image should beno greater than 50 nm.

Although particular embodiments of the invention have been described indetail, it is understood that the invention is not limitedcorrespondingly in scope, but includes all changes, modifications andequivalents coming within the spirit and terms of the claims appendedhereto.

1. A method of fabricating an integrated circuit on a wafer using dualmask exposure lithography, comprising: forming a photo resist layer overthe wafer; aligning the wafer with respect to a lithography system usinga reference mark that is formed on the wafer; exposing the photo resistlayer with a first mask image defined by a first mask using thelithography system, the first mask image including a latent imagealignment mark that is transferred to the photo resist layer;re-aligning the wafer with respect to the lithography system using thelatent image alignment mark resulting from the exposure to the firstmask image; exposing the photo resist layer with a second mask imagedefined by a second mask using the lithography system; and enhancingdetectability of the latent image alignment mark to an alignment sensor,wherein the enhancing includes developing a portion of the photo resistlayer after exposure by the first mask image to establish a latent imagealignment mark edge in the photo resist layer.
 2. The method accordingto claim 1, further comprising developing the photo resist layer afterexposure with both the first mask image and the second mask image. 3.The method according to claim 2, further comprising using the developedphoto resist layer to protect a layer underlying the photo resist layerfrom at least one of etching, implantation and chemical reaction.
 4. Themethod according to claim 1, wherein the lithography system is selectedfrom a step-and-repeat lithography system, a step-and-scan system andcombinations thereof.
 5. The method according to claim 1, wherein thelithography system includes a first alignment sensor for tracking alocation of the reference mark and a second alignment sensor fortracking a location of the latent image alignment mark.
 6. The methodaccording to claim 1, wherein the enhancing includes adding a compoundto the photo resist layer during photo resist formation such that thephoto resist layer changes appearance in locations exposed to athreshold amount of energy as defined by the first mask image.
 7. Themethod according to claim 1, wherein the photo resist layer includes atleast two sublayers and the developed portion of the photo resist layerincludes a top layer of the sublayers.
 8. The method according to claim1, wherein the first mask image and the second mask image create acomposite mask image on the photo resist layer.
 9. A method offabricating an integrated circuit on a wafer using dual mask exposurelithography, comprising: forming a photo resist layer over the wafer;aligning the wafer with respect to a lithography system using areference mark that is formed on the wafer; exposing the photo resistlayer with a first mask image defined by a first mask using thelithography system, the first mask image including a latent imagealignment mark that is transferred to the photo resist layer;re-aligning the wafer with respect to the lithography system using thelatent image alignment mark resulting from the exposure to the firstmask image; and exposing the photo resist layer with a second mask imagedefined by a second mask using the lithography system; wherein the photoresist layer includes at least two sublayers and exposure by the firstmask image results in latent image alignment mark detectability in atleast a top one of the sublayers.
 10. A method of fabricating anintegrated circuit on a wafer using dual mask exposure lithography,comprising: forming a photo resist layer over the wafer; aligning thewafer with respect to a lithography system using a reference mark thatis formed on the wafer; exposing the photo resist layer with a firstmask image defined by a first mask using the lithography system, thefirst mask image including a latent image alignment mark that istransferred to the photo resist layer; re-aligning the wafer withrespect to the lithography system using the latent image alignment markresulting from the exposure to the first mask image; exposing the photoresist layer with a second mask image defined by a second mask using thelithography system; and enhancing detectability of the latent imagealignment mark by increasing exposure of the latent image alignment markwith the first mask image.
 11. The method according to claim 10, whereinincreasing the exposure includes exposing at least twice with the firstmask.
 12. The method according to claim 10, wherein increasing theexposure includes exposing with an overlapping exposure.
 13. A method offabricating an integrated circuit on a wafer using dual mask exposurelithography, comprising: forming a photo resist layer over the wafer;aligning the wafer with respect to a lithography system using areference mark that is formed on the wafer; exposing the photo resistlayer with a first mask image defined by a first mask using thelithography system, the first mask image including a latent imagealignment mark that is transferred to the photo resist layer;re-aligning the wafer with respect to the lithography system using thelatent image alignment mark resulting from the exposure to the firstmask image; and exposing the photo resist layer with a second mask imagedefined by a second mask using the lithography system; wherein one ofthe first mask image and the second mask image defines criticaldimension structures and the other of the first mask image and thesecond mask image defines non-critical dimension structures.
 14. Amethod of fabricating an integrated circuit on a wafer using dual maskexposure lithography comprising: forming a photo resist layer over thewafer; aligning the wafer with respect to a lithography system using areference mark that is formed on the wafer; exposing the photo resistlayer with a first mask image defined by a first mask using thelithography system, the first mask image including a latent imagealignment mark that is transferred to the photo resist layer;re-aligning the wafer with respect to the lithography system using thelatent image alignment mark resulting from the exposure to the firstmask image; and exposing the photo resist layer with a second mask imagedefined by a second mask using the lithography system; wherein one ofthe first mask image and the second mask image defines edges in a firstdirection and the other of the first mask image and the second maskimage defines edges in a second direction transverse to the firstdirection.
 15. A method of fabricating an integrated circuit on a waferusing dual mask exposure lithography, comprising: forming a photo resistlayer over the wafer; aligning the wafer with respect to a lithographysystem using a reference mark that is formed on the wafer; exposing thephoto resist layer with a first mask image defined by a first mask usingthe lithography system, the first mask image including a latent imagealignment mark that is transferred to the photo resist layer;re-aligning the wafer with respect to the lithography system using thelatent image alignment mark resulting from the exposure to the firstmask image; exposing the photo resist layer with a second mask imagedefined by a second mask using the lithography system; and at leastpartially developing the photo resist layer between exposing with thefirst mask image and the second mask image.